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asic fpga resume Seeking a challenging and rewarding contracts in ASIC/FPGA Design Verification. Overall experience of over 10 years in myer holdings ASIC/FPGA Design/Verification Verified Fibre Channel - 1 and Fibre Channel Arbitration Loop RTL Developed TCP/IP Functional Models in SystemC and verified the personal examples TCP RTL implementation Designed and Verified ZBT SRAM and Flash interface for LEXRA RISC Processor Designed and Verified a Ingress FPGA [Virtex II] for Nortel s Gigabit Ethernet line card Verified SPI-4 Soft core and myer holdings, Synthesised the same towards Virtex II FPGA Designed and Verified USB1.1 Serial Interface Engine SOC Integration of a Smart Card ASIC Participated in the development of a VHDL Simulator. Languages : VHDL / Verilog HDL, PERL, SystemC, Vera, C, C++ Simulators : NC Verilog, Verilog XL, ModelSim VHDL/Verilog simulators Synthesizers : Synopsys Design Compiler, FPGA Express, Leonardo Spectrum,Xilinx Implementation Tools, Synplicity Memory Compilers: Denali Pure View Foundry Tools : Samsung s Foundry tools Cubicware Protocols : TCP/IP, Gigabit Ethernet, Fibre Channel [FC - 1,FC - Arbitrated Loop], SPI-4, USB1.1, EP1284 and ISA. M.S. Electrical and Electronics Engineering. Created a detailed test-plan to geographic, verify the Fibre Channel [FC - 1 and FC - Arbitration Loop] RTL and verified the RTL as per the test plan Designed a Word Builder for the FC -1 block, integrated in the FC-1 RTL and verified the same. Verified the RTL implementation of myer holdings, TCP/IP Stack.

A detailed test plan was created and The Patient Griselda, by Giovanni Boccaccio, SystemC models of the functional blocks were written to test the whole of TCP/IP Implementation. Myer! Designed and verified the LEXRA RISC Processor Interface with the functional blocks and verified the same. Designed and verified the ZBT SRAM and Flash interface for the Lexra RISC Processor. Integrated all functional RTL modules and personal swot examples, created a system level top. Perl scripts where written to manage the files and test cases. Created the myer holdings Vera testbench environment for the whole chip.

Modified the SPI-4 soft core both on the Sink and Source data paths. Synthesized the modified RTL code on Synplifypro and why is a sin, implement the netlist on Xilinx Implementation tools targeting to Xilinx virtex II series. Verified the holdings RTL and post layout netlist for functionality and timing. Swot Examples! Ingress FPGA for line card: Designed and implemented the Network Processor interface on the Ingress traffic flow towards the myer holdings Switch fabric. The module also implements policing, segmentation, Packet format modifications and tora!, sends the packets across to the switch fabric. Synthesizing the modified RTL code on Xilinx Implementation tools targeting to Xilinx virtex II series XC2V3000 . Gate count of the myer holdings complete Ingress FPGA 1,800,000 gates.

Modified the Accelar Simulation Environment Nortel functional simulation environment used for Verification used the same to verify the modified RTL code and synthesized gate level netlist. The job involved understanding the john Accelar simulation environment and myer, modifying the same in accordance with the new requirement. Verified the synthesized code on the Modified Accelar regression simulation environment. Why Is Fornication! Trojan ASIC - USB Smart Card Solution: Synthesized the DesignWare 8051 of Synopsys Inc towards Samsung 0.35u STD90 technology on Synopsys Design Compiler. Designed testbench to test the DesignWare 8051 functionality.

Mapped to whole design to XILINX FPGA - virtex series - using the Exemplar s Leonardo spectrum and Xilinx M1 implementation tools. The pre-layout and post-layout simulations were done on MODELSIM simulation environment. SOC integration of myer, Synopsys DW8051, Smart Card Interface chip, SIE USBC core. Project managed the whole simulation work of the USB-Smart Card. Enhanced already present Smart Card Device Model.

Responsible for why is a sin, testing debugging of the functionality of the design. USB SIE Serial Interface Engine : Designed tested of all the modules of Serial Interface Engine. Project managed the myer whole simulation work of the Serial Interface Engine. Integrated the SIE with the USBC and Mapped the whole design to XILINX FPGA - 4000XL series - using the Exemplar s Leonardo spectrum and profiler, Xilinx M1 implementation tools. The pre-layout and post layout simulations were done on MODELSIM simulation environment. Responsible for testing debugging of the functionality of the SIE USBC design. Ultimate - VHDL simulator conforming to IEEE VHDL specification : Took part in the kernel development of the simulator. Design and implemented an intermediate format for the simulator. Wrote extensive test cases to test the various constructs and expressions of VHDL according to SPEC defined by IEEE. References Furnished Upon Request. Development simulation/verification or design on holdings high speed electronics.

VHDL, C, MTI simulator, ModelSim, RiscWatch debugger. Digital Corp. San Jose, CA. Hardware Development Engineer. Modified behavioral VHDL logic of an The Patient Griselda, by Giovanni Boccaccio existing PowerPC 603 cpu simulation model to holdings, communicate between an ASIC and blake persuasive writing, a C code simulator, including the holdings addition of decoders, latches, and education writing, state-machine modifications. Designed VHDL logic code that enhanced the 603 cpu model by generating an internal address bus busy signal when an address-only phase is myer holdings, initiated by the ASIC. Developed 200+ C testcases for functional simulation, system level stressing and debugging of the ASIC s internal logic, including cpu and pci address space, SRAM, cache, BAR and other registers. Co-developed C code for why is a sin, parity generation on a PowerPC 603 address bus and the ASIC s read-only cache register contents. Developed test plans to verify functionality of the ASIC s internal cache, and its 603 bus logic.

Board-level timing analysis and measurements of setup, hold, output valid times, overshoot, undershoot signal quality, frequency voltage margining for various end-of-life replacement chips on a Fiber-channel to PCI I/O adapter board used in high-end data storage servers. Simpson Communications Corp. Myer Holdings! White Lake City, UT. Hardware Development Engineer. Designed, functionally simulated, and personal swot, synthesized, using PC-based ModelSim, RTL VHDL code, that converts a serial bitstream of data into bytes, then calculates the myer holdings average byte value from 16 bytes of data. Translated PAL gray-code state machine and counter ABEL equation designs into behavioral and structural VHDL code then functionally simulated using Unix-based Synopsys tools. Translated gray-code state machine and tora! tora!, counter state graph designs into RTL and holdings, structural VHDL code then functionally simulated, using PC-based Xilinx Foundation Series and ModelSim tools. Developed a C code program that calculates a least-sum path of distances squared for a trade study that will implement ATM networking hardware on a RF communications data link. Researched and wrote a white paper about Voice over john collier ATM using AAL1 CBR, AAL2 rt-VBR AAL5 services and implementing G.711 PCM, G.726 ADPCM, G.728 LD-CELP, and G.729 CS-ACELP ITU-T voice compression standards, for holdings, networking over a RF communications data link.

Amtel Corp. Boxsboro, OR. Configured and validated the compatibility of various PCI and EISA LANs and the chaser collier, SCSI controllers and devices on quad Pentium-Pro Servers. ADDITIONAL JOB EDUCATIONAL TRAINING: Fiber Channel, ATM VHDL course designing a 16-bit alu w/pipelined registers Analog RF/microwave theory, device physics theory, and CMOS VLSI design coursework COMPASS, SPICE, Touchstone/Libra, Fortran, Mentor, Viewlogic, FPGA Express and Synopsys tools. Myer Holdings! ME Electrical Engineering, University of Utah, Salt Lake City, UT. BS Electrical Engineering, University of Utah, Salt Lake City, UT.

TO PUT MY EXTENSIVE ENGINEERING SKILLS TO WORK FOR YOU. TARGET JOB: Telecommunications, Medical, Underwater Research and R D. Target Job Title: Engineering Manager. Alternate Target Job Title: Senior Electrical Engineer. Desired Job Type: Employee, Temporary/Contract/Project. Desired Status: Full-Time. Desired Salary: 95,000.00 USD Per Year. Geographic! Site Location: On-Site. Holdings! Job Title: SENIOR ELECTRICAL ENGINEER/TECHNICAL/ENGINEERING MANAGER. Profiler! Career Level: Management Manager/Director of Staff.

Date of Availability: Immediate. TARGET COMPANY: START-UP IN EITHER TELECOMMUNICATIONS,SCIENTIFIC R D or MEDICAL EQUIPMENT R D. Myer! Company Size: Prefer small. Category: Electrical Engineering. TARGET LOCATIONS: Will Relocate with conditions. WORK STATUS: UNITED STATES I am authorized to work in this country for any employer. Have held Security Clearances. Valid MASS Drivers License Class 3. Assigned tasks, maintained cost and why is, schedule to a group of 20 Engineer and Manufacturing Personnel. Provided upper management monthly Progress Reports and Weekly Departmental updates.

Interacted with all required agencies, vendors, and holdings, customers to persuasive, meet corporate objectives and deadlines. Extensive expertise in the Engineering Process. Highly skilled in myer holdings Product Design Development of personal swot, Electro-Mechanical Products. Participated in providing Technical Engineering Leadership and Support to System, Concept, Equipment, Readiness and Production Review in Transiting new Designs into a Solid Product. Myer Holdings! Developed and Documented Specifications, Concept Definitions, Analyses and Trade Studies of various Electro-Mechanical Systems.

Highly Knowledgeable of CAD Systems in generation of tora!, Assembly Dwgs., Parts Lists, Detailed Dwgs. Altered Item Dwgs. Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required. Extensive hands-on experience in System Debug Component Level Troubleshooting, Electro-Mech Assembly, Integration Test, with wire-wrap and soldering expertise. Integration and Test of a variety of myer, Computer Hardware. PROFESSIONAL WORK EXPERIENCE. SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA. Assistant Store Manager/Customer Service Rep. Providing management assistance to Store Manager. Responsible for opening and closing.

Assignment of daily retail task and examples, scheduling of available manpower. Providing customers with benefits of my expertise in the Art of holdings, Woodworking. Upgraded and swot examples, re-merchandise entire store increasing net sales by 30 . Myer Holdings! Have sold well over 250,000 woodworking tools in 8 months. Tora!! MILLERVILLE PHOTO PROCESSING CAMERA, Inc. Millerville, MA.

Photo Lab Technician/Customer Service Rep. Processing and developing all types of Photographic Media including Digital Photography. Handing of Customer questions and accountable for cash flow. Expertise acquired in myer the service and maintenance of Fuji Photo Processing Equipment. Generated documentation of all Photo Processing and Printing Procedures. Adhered to EPA Hazard Waste Requirements. COMPUTER AIDED SYSTEMS Boston MA. Consultant Electrical Engineer/Electronic Technician. Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of geographic profiler, PLC Interfaces using OrCAD.

Performed various Test Engineering activities. Involved in assessing and performing the overall Functional and In-Circuit Test activities in myer the production and repair of the DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and personal examples, associated Power Supply SMD Assembly. Holdings! Performed evaluation and refinement of a variety of Functional Test operations, debug analyses and recommended solutions to improve the production through-put and provide fully tested hardware to the customers of contract manufacturing firms. Created Final Test Procedure for the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards. Documented and tora! tora!, Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Myer Holdings! Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly Progress Reports and Weekly Departmental updates.

Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. By Giovanni Boccaccio! Managed and participated in myer Electrical Engineering involved in the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for the daily technical operation and security functions of the DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and by Giovanni Boccaccio Essays, maintained PATRIOT COMO Simulation Laboratory. Myer Holdings! Technical Integration Lead to an engineering group of the chaser collier, 10 engineers, in both hardware and software. Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration. Technical Lead Integration Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and tested a number of holdings, VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to production and on through qualification testing at Field Sites. Technical Lead Electrical Engineer for swot, PATRIOT COMO UPGRADES participated and provided input to System, Concept, Equipment, Readiness and Production Reviews.

Assistant Subcontract Manager for Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO. Development Engineer 1990-1992. Holdings! Electronic Design Laboratory Lead Engineer and Cost Account Manager for a sin, TACIT Rainbow Mission Computer TRMC . The TRMC is based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply. Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and Production Reviews transiting the myer holdings TRMC Design into a solid Product with the personal swot examples help of myer holdings, Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of why is fornication, various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. Holdings! as required.

Built, Serviced and Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and collier, Silicon Graphics Workstations in the performance of software code development, system simulation and software performance evaluations. TRMC 80 Logic in Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and myer holdings, Manufacturing resources into developing a fully integrated, form-factored and tested unit which was integrated into the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. The Chaser John! Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and holdings, Cost Account Manager. Provided upper management monthly progress reports and weekly departmental updates. Assigned design tasks and geographic profiler, maintained cost and schedule. Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for myer, F15/F16/F18. Provided User Interface ports Monitor, Serial and Parallel Printer interfaces.

Tested and qualified to john, MIL-STD-810C 12 units. Lead Engineer for Missile Integration Test Set MITS Integrated, incorporated and tested Short Round Test Set into MITS H/W to provided Full-Up Missile Test. Lead Engineer for Dynamic Software Test Facility DSTF for software development designed, developed, integrated and tested a facility based upon myer holdings five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of Personal Computers. Electrical Engineer 1986-1987. Module Design Engineer responsible for all components of the Module Design Process. Coordinated and supplied technical design input, integration test and operational inputs for examples, innovative subsystem development.

Redesigned the Digital Signal Processor and upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and the other a Aircraft HOW Interface Module 50 Analog as part of myer, Low Cost Seeker Program HARM. Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and VHDL PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc.

Boston MA. Senior Electronic Design Engineer. Personal! Performed and Specified the myer Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and Testing of a Computerized Newspaper Pagination System for a sin, a start-up company. Myer! Product Line developed and by Giovanni Essays, marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and BitPlater Laser Platemaker . Holdings! Involved in all phases of electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon the AMD2903 Bit-slice processor form factored on a 12 x 12 multi-layer PWB using inverse euro-connectors. Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic. Swot! Used Future Net and Multi-wire prototyping. Holdings! Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the i ncorporation of a wide range of Off-the-Shelf Multibus I Modules.

DAYNEON COMPANY, Bedford MA. Test Engineering Aide. Tora! Tora!! Worked in the Missile Integration and Test Department of the Missile Guidance Laboratory while attending NU. Assisted in myer the integration and testing of the prototype AMRRAM Missile. Involved in the development of a Missile Readiness Test Set MRTS . Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings.

Oversaw building of unit and performed engineering inspections;Performed initial testing and qualification testing. Profiler! PANAMETRICS Inc., Waltham MA. Design Engineering Aide. Under direction of Physicist and Electrical Engineers worked as a member of the Radiation Physics Laboratory while attending NU. Performed tasks in Prototyping, Development and Testing of myer, various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college.

Worked as Security Guards, Cashier at geographic Store24, Retail Sales at myer holdings Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and Landscape Business. The Chaser John! 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON. Bachelor s Degree BS ENGINEERING TECHNOLOGY. 1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS. 1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE.

Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and holdings, SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of the chaser john, a variety of holdings, computer hardware; Familiarity with Test Equip./ATE. Personal! PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in Ethernet/firewall product development for the OEM customer base. Designed the architecture for the current ASIC Ethernet hub/switch. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and myer, 24K of Dual Port SSRAM using .25-micron technology. Headed the tora! design team in the implementation of the chip. VHDL was used for the design implementation.

Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into myer holdings, an Actel FPGA that was used on the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and the chaser collier, an ITE PCI bridge. In charge of engineering development of board level designs for both product and OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Wrote guidelines for myer holdings, PCB layout that encompasses component placement for high-speed signals and FCC compliance testing. Incorporated manufacturability into designs including ATE. Developed and maintained project schedules.

Interfaced with the software department for geographic profiler, BIOS and POS functionality. MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to February, 1999. MANAGER OF ENGINEERING. Manager of the hardware engineering team.

Involved in product planning for a new family of holdings, OEM image processing controllers. These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of product development, resource management, project management, ASIC vendor selection and CAD tool evaluation and purchasing decisions. Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and vendor coordination. Also, designed the system architecture for a second ASIC that became the system intelligence. This contained an embedded ARM7 processor, PCI interface, DRAM, etc. Why Is! Led the myer design efforts on personal this second ASIC. Both ASICs were in the 1M to 1.5 M gate range and implemented in .25-micron technology.

VHDL was used for the design implementation. Designed several controller boards that used these ASICs for different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to December, 1997. MANAGER OF ENGINEERING. Managed the Raid Division engineering team. Responsibilities included scheduling, budgeting and product development for both board and system level Raid products. Myer! Involved in defining the next generation architecture of Raid controllers that was comprised of a four ASIC chip set.

Project Manager for a Digital Equipment Corp. specific Raid controller. This project was a joint effort between CMD and Digital with CMD designing the controller and personal swot examples, Digital doing the myer holdings mechanical packaging. Responsibilities included coordinating the hardware efforts between the two companies along with designing a FPGA that interfaces to Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital. Designed several other Raid controller boards that were used for the OEM market.

Member of the Change Control Board CCB and john, the Advanced Products Group. Involved in implementing procedures between Document Control and myer, Engineering. The Patient Griselda, Boccaccio Essays! CORSER CORP., Costa Brava, CA. Myer! May, 1992 to June, 1995. Involved in the design of a DAT tape controller ASIC which interfaced to a SP1 format tape drive. This ASIC was implemented in .8-micron technology.

Designed the next generation DAT tape controller ASIC. This chip was implemented in education persuasive writing .6-micron technology and has approximately 80K gates. Myer! Designed the tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of DRAM buffering and FLASH EEPROM. Joined the Arcuate Scan Tape group and designed an ASIC used in controlling the tape head preamps. This ASIC was mounted to the head assembly using chip-on-board technology. Tora!! Also designed the Servo Gate detection ASIC used for head positioning. All ASICs designed and simulated at Conner were done using VHDL.

IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to April, 1992. MANAGER OF ENGINEERING. Management responsibilities for holdings, engineering, software, and test departments. Established procedures in top-down design methodology and functional specifications for the Software and Hardware Departments. This provided a path for designs with a high degree of modularity and ease of software/hardware integration. Defined future products and initial marketing strategies. Designed a proprietary Error Detection and Correction ASIC to be used in memory intensive products.

A 16 and 32 bit version of this ASIC was designed in 1-micron technology and consisted of 34K gates. Examples! CAD tools used in these ASIC designs include Cadence for schematic capture and Verilog for simulation. Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Involved in setting up incoming test procedures for partial memories using a Teradyne tester. Two patents emerged from the research of memory subsystems. Holdings! FUTURAMA, Sacramento, CA. October, 1984 to November, 1988. PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system.

Interfaced with the why is fornication a sin software development group to identify areas of concern when porting UNIX on to the new system. Myer Holdings! Designed a 68000 based CPU board for this development system. During the design phase of the personal examples CPU, research was done on interfacing a 68000 to myer holdings, various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the system protocol that provided an efficient means of communication between the CPU and tora!, intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol. TRIANON CORPORATION, Sacramento, CA. Myer Holdings! March, 1981 to October, 1984. PROJECT MANAGER/SENIOR ENGINEER. Project Manager for profiler, the Mark III minicomputer. Myer Holdings! Responsibilities included managing an engineering team and coordinating the software and manufacturing departments efforts on the project.

Designed the hardware and firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface. The Peripheral Interface Board was designed using discrete logic and incorporated the 2903 bit slice architecture for the micro-engine. The firmware consisted of 32 bit-wide microcode. The Chaser! COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to March, 1981.

Engineering team member involved in the development of a new processor and the related I/O controllers. Holdings! Designed the interface protocol and an I/O relay controller for this processor. This team was located in fornication a sin Dallas, Texas. Previously: Designed a debug module including hardware and holdings, firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon receiving a pre or post trigger. The back-end contained the necessary handshaking to a modem so the board may be used remotely from the operator. Initial assignments upon joining the company involved sustaining engineering hardware and fornication a sin, firmware for a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977.

Concentration in Computer Systems. Will be furnished on request. Six years of strong experience in research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and micro controllers. Expertise in design and simulation of myer, electronic circuit boards using orcad, spice, circuit maker and smart work. Expertize on Active HDL simulation package. Profiler! Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice. Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer.

September 2001 - Till date. Development of a stand alone device to measure moisture content of various agricultural products. Myer! Involved in Design and development of automatic moisture meter both independent and computer interfacable. First prototype developed around 8051 microcontroller using AVC 51 for embedded system. Involved in sensor design. Design and swot, coded same using C. Holdings! Handled design and geographic profiler, fabrication of myer holdings, analog and digital boards for first prototype.

Second prototype being developed as full custom SOC System on chip for the calibration circuit around microcontroller 8051using simulation and synthesis tools of personal, mentor graphics. The input taken by sensor directly displayed in terms of myer holdings, percentage moisture. Persuasive Writing! Development of calibration technique based on method of least squares. Writing source code and test benches in VHDL for myer, interfacing of 64K RAM, ROM, decoder and their interfacing with the blake education A/D converter and PGA. Simulation of calibration process and verification of functionality and timing errors for same. Synthesizing code on myer holdings Xilinx virtex series using Xilinx FPGA. Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization.

8 BIT Microcontroller ASIC Design Engineer. Involved in design of a 8-bit micro-controller having features of INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and personal swot, is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in myer VHDL. Profiler! Wrote source code for the ALU to perform various arithemetic and logical opeartions. Source code for myer, the RAM and ROM entity was written and geographic, debugged using test bench generation schemes. A complete model of the FPGA was designed using the above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. Myer! a memory mapped output port was also added to the design. Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools. Central Scientific Instruments Organization. Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to operate at 2.5 GHZ using spice simulation software.Involed in the chaser counter design for the programmable counter for the magnetron switching circuit. Involved in myer holdings debugging, verification and analysis of critical timing parameters for education persuasive, low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and critical path parameters.

Environment: Spice simulation software for mixed mode signals, Mentor graphics simualtion and synthesis tools. Department of Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and was simulated for various digital applications. Holdings! Captured top-level video inputs simulation of VMIS video million images per second TV controller chip having an embedded processor. Enabled signal processing for digital applications.

Worked in a team for simulation of profiler, chip. Holdings! Carried out chip verification using using tools from geographic mentor graphics. Verified ASIC for rtl resistor transfer logic syntax and semantics. Myer! Used Configuration Management Tool for database version control. Environment: Embedded processor from sigma Electronics, Mentor graphics tools, VHDL, Windows 98. Technology mission for oil seeds and pulses. Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of various samples to be measured for different parameters.

The selection of photodiodes was done to opearte at radio frequencies. Designed analog and digital board around SPICE simulation software. Interfaced memory and display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051. Further, an FPGA was developed to perform the application of microcontroller 8051 and the entire calibration circuit was interfaced around the Xilinx FPGA. Coded using VERILOG.

The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . As a team member wrote source code for The Patient Griselda, by Giovanni Boccaccio, the FPGA microcontroller features and tested the functionality of interfacing circuit and simulated it using modelsim VERILOG. Holdings! Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts. Examples! Department of Science and Technology DST. CPU Central Processing Unit Design ASIC Design Engineer. Designed and developed a 8-bit microprocessor.

The device consists of a RAM, ROM, a high speed ALU, shifting, decoding and multiplexing circuitry. Made package for holdings, the instruction set of john, 8085 in VHDL. Holdings! Wrote source code for the ALU to perform arithmetic and logical operations using VHDL, source code for the RAM and blake education, ROM implementation. Simulation of the functionality of the processor using test benches on Active HDL simulation package in Window NT environment. synthesized the same on XILINX FPGA. Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of Oil seeds and Pulses. Digital aflatoxin meter Test Engineer. Designed electronics related to myer holdings, system around ORCAD IV , checked for personal examples, the functionality of the design using mixed mode signal simulation around ORCAD IV and development of calibration software around microprocessor 8085. Documented instrument for transfer of know how and providing intensive training to user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085. Department of science and technology.

Sept 1996- March 1997. Gold Analyzers Test Engineer. Myer! Developed analog and digital electronics design circuit board using ORCAD. Checked the functionality of the same and its interfacing with the sensor. Documentation of The Patient Griselda, by Giovanni Boccaccio, instrument.

Involved in selection of principle of purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry. Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Responsible for holdings, integration and test of a UART, real time clock, keyboard controller, DMA controller and interrupt controller chip. This helped in gaining good understanding of ASIC design and verification methodologies along with PAL and FPGA programming.

Responsible for working with clients on tora! tora! tora! intensive short term methodology training. Holdings! Responsible for training students in geographic profiler VHDL, synthesis and myer, methodology. Aid in adaptation of training materials and development of new training classes. Paper publications and presentations have been made on Digital Automatic Moisture Computer and Capacitive moisture measurement of grains and oil seedsin various national journals. Training has been imparted to various engineers and students of engineering colleges from time to time. Significant contribution in organization of various seminars and conferences related to instruments developed, various projects for water quality monitoring and soil analysis have also been designed and developed. B.S. in Electronics Engineering.

Assume a role in ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry. Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for a TtME (Time to Market Engineering - a design verification consulting service) project for a Germany based company. Fornication A Sin! Successful completion of the project lead to the sale of an myer emulation system. Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and profiler, VHDL) through synthesis and simulation, providing training implementing Cadence verification tools on site.

Used test benches for myer, passing vectors and debugging simulation differences. Implemented Verification Flow. Identified introduced Cadence tools to the Verification process. Tora! Tora!! Advised on design methodology and validated the subsequent setup. Lead Engineer for holdings, a European account (Philips - HDTV division): Consulted on Verification flow, and provided optimization ideas. Geographic! Offered on site support and tool integration. Myer! Implemented a synthesizable cycle based design and test bench, and helped with the execution. Assisted in why is customer evaluation (San Jose based IC design company for DTVs) for a simulation acceleration beta product. Worked with verification engineers to write optimized test benches. Worked on a product evaluation with Ericsson, Sweden, that resulted in sales for holdings, numerous simulation software licenses.

Worked closely with Quickturn RD and personal, a third party RD (Verisity) that provided the testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. Worked with QT and myer, Verisity s RD to integrate all of these products. Provided post-sales technical support and worked to increase the simulation performance. Used profiling tools to personal, determine simulation speed bottlenecks. Implemented RTL and C model design changes for myer holdings, maximum performance optimizations. Successfully completed a TtME project with Ericsson, Germany, over tora! tora! tora! a four-month period. This involved remodeling (in Verilog) significant portions of their design, testbench and memory models to be cycle based. Debugged differences in simulation results between Speedsim and the customer s internal simulator. Successfully completed a two-month TtME project with Cabletron.

Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and making the LogicVision environment compatible to Speedsim. Assisted the Quickturn India Distributor with a customer evaluation. Myer Holdings! Responsibilities included going on tora! tora! site and using test bench methods, passing vectors for showing proof of Speedsim functionality and performance on their design. Holdings! Provided training to Application Engineers on topics related to simulation/acceleration tools during boot camps and other training sessions. Worked on personal examples numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and emulation tools. Presented demos and holdings, presentations at DAC 98 and a sin, DAC 00. Corporate Technical Support Specialist: Provided technical support for holdings, all of tora! tora!, Quickturn s Simulation/Acceleration products.

Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and holdings, Mitsubishi. Tora!! Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and questions. Providing workarounds to customer issues and working with RD to get critical customer bugs fixed as soon as possible. Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in VHDL. The unit included microprocessor and holdings, memory components. Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96.

B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in Cadence Simulation, Acceleration and personal, Synthesis Tools. Experienced with ViewLogic Schematic, Design and Waveform Viewer tools. Holdings! Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace. Strong Verilog skills, VHDL, C, Unix, Perl. References available on request. ASIC PHYSICAL DESIGN ENGINEER. The Chaser John! To achieve excellence, to be resourceful and optimistic and to pursue a challenging career in VLSI design. Area of specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in myer holdings short : Have got more than 20 months of experience in the field of VLSI. John Collier! Worked in logical design for 8 months rest in myer holdings physical design.

Moreover i have done my academic project in VLSI field. Arsanti! Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Used to create testcases for QA of Avanti tools. Creating testcases to check various releases of Avanti tools. Geographic Profiler! Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer. Responsiblities : Logical design Digital design. Writing Verilog codes for various small Designs.

Writing Test benches for designs. Writing Scripts to check the designs. Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for circuit implementation and myer holdings, test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of Griselda, Essays, Top Cell with core utilization of 75%, alongwith floorplanning of each soft macros with utilization of 80%. Holdings! (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns. The CTS is carried out for the Top Cell also. Why Is! (Tool used ApolloII).

Routing of each macro and the Top Cell. (Tool used ApolloII). Physical Verification for DRC LVS for each macro and the Top Cell. (Tool used Hercules). Myer Holdings! Company : TTM( as a part of training program in Physical Design) Designing of Standard Cells of tora! tora!, 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of holdings, 98.5%. The Patient By Giovanni! Contains 19 hard macros, and 28k standard cells. Holdings! (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an initial slack of tora! tora!, -61.3, and congestion overflow of 4.03%. (Tool used ApolloII Saturn) BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2.

Bench Mark for Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to holdings, meet. Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout Its mearly an analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP) EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the true computer on chip.The design incorporates all of the features found in a microprocessor ie. Fornication! CPU,ALU,SP,PC,genaral purpose registers and myer holdings, special purpose registers.It also has added the other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is meant to read data, perform limited calculation on personal that data and controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and RAM. POLARIS for simulation. Myer! EXPLORERTL for RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and blake persuasive, testbench had been written for all the above units.Various stimuli had been given and the logic had been validated.

TOOLS USED : simulator : MODEL SIM PE 5.3b. DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry. 10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and myer, Behavioural. Geographic Profiler! Assembly languages : Microcontroller. Software languages : C. Operating Systems : Unix,Windows.

Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious. Myer! A go-getter. The Chaser John Collier! Quest for perfection in all assignments. Date of Birth : 02-08-1977. Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment.

Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date. Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN. Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for holdings, Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and MPC8260 Motorola Power PC via its Local Bus. The Patient Griselda, By Giovanni Boccaccio! HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC).

KHATANGA is a dense VLSI device developed by myer Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of collier, Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA. Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for myer holdings, Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA. MPC8260 wrote overhead byte information into personal, FPGA memory locations defined for those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by MPC8260. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of Frame, Bit Parity Errors (BIP) and reported them to MPC8260. Myer Holdings! Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and fornication a sin, developed architecture for full functionality of the chip. Automated critical parts of design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5).

Involved in myer synthesis of modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT. Contesse Semiconductor Corporation. Education Writing! October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface. Myer Holdings! Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Transport OverHead (TOH) and personal swot examples, Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in myer holdings a Time Division manner.

The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to corresponding Spectra155 devices. Similarly overhead data that is sent by Spectra155 device is sent to HMVIP interface in personal examples correct time slot at holdings correct frame location. The Chaser John Collier! There are eight dual port asynchronous RAMs implemented in this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of chip. Coded transmit side modules of this architecture in Verilog HDL and tested functionality and performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Myer! Used Xilinx synthesis tool for examples, synthesis of design and generating sdf file.

Did post-synthesis simulation of this design. Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an FPGA to convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to holdings, Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip. Persuasive! Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to convert data (packets) from one bus protocol to other.

Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to carry Fcells in both receiver and transmit side. Holdings! Did regression testing of Verilog RTL code. Generated random set of Griselda, Boccaccio, valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of test cases from the holdings valid testcase library using a seed value. Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface. This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to personal swot, UXGA and to holdings, even support SXGA+ and W-UXGA.

Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for tora!, digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in digital architecture design of myer holdings, chip. Coded the entire architecture in geographic profiler VHDL and holdings, did functional testing and simulations of fornication a sin, code. Used Shell Scripts for taking test bench (testing file used to test functionality of holdings, VHDL code). Used Synopsis DC for synthesis.

Performed post-synthesis simulations. Tested and verified actual performance of chip on blake education writing LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1. May 1999 - November 1999. Design of Flying Adder Digital Logic for PLL (TFP8501) Chip. Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in myer holdings design of Digital logic for Flying Adder PLL (50MHz to geographic profiler, 350MHz). Myer! Did coding of digital logic in VHDL. Performed synthesis of design using Synopsis DC.

Used SPICE for profiler, analysis the analog behaviour of timing critical nets. Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1. January 1999 - April 1999. Myer! Design of Analog PLL. Involved in the design of a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection. Rate of writing, video data transfer on TMDS channel is 1.6Gbps. It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz).

Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO. Used Cadence Artist and Spice for analog design. Carried out myer holdings all process corner simulations of individual design modules and completed closed loop simulations of why is fornication a sin, PLL. Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. Myer! October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in tora! the Design of a TMDS receiver core chip for holdings, LCD monitors. It supports Transition minimized Data Signaling protocol from personal swot PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to myer holdings, be entirely digital.

Designed and coded the architecture for the chaser collier, Power Management Module in myer VHDL. Did synthesis of this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998. Design of geographic profiler, Single Phase Energy Meter. Designed and developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Did assembly language programming of myer, design.

Successfully tested design on power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. S. in Microelectronics and VLSI Design. ASIC/FPGA Design Verification Engineer. Swot Examples! 2.6 years of experience in FPGA Design ASIC Verification. Proficient with coding RTL Behavioral using Verilog and VHDL. Proficient with developing test environment for functional verification. Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language.

Proficient in writing fully automated test benches. Myer! Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx. Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys). Worked on Mentor Graphics Schematic Entry Tool Design Architect. Worked on PCI 32 bit @33Mhz Worked with Specman, an ASIC Verification tool from Verisity Familiar with Vera, an fornication a sin ASIC Verification tool from Synopsys Familiar with DSL Protocol. Familiar with ATM Protocol. Familiar with AMBA Bus Architecture. Familiar with 8085 and 8086 Architecture. Holdings! Familiar with 8085 Assembly Language. Familiar with software languages C and blake writing, Fortran. Good communication skills.

ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Myer Holdings! Name of fornication a sin, Project: Network Processor Verification. Wrote test plan for one of the modules in the chip. Developed the test bench for the module. Wrote test cases in Verilog. Developed the different interfaces around the module.

This network processor is designed to provide solution for 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA. Designed and myer, Synthesized SWATH cycle Controller module. RTL coding done in Verilog with Verilog-XL and tora! tora!, Synthesized using Synplify Developed the holdings different interfaces around the Link 2 FPGA. Profiler! Developed test plan for the functional verification and wrote test cases in Verilog. Done the module level verifications and top-level verification. Reported bugs and worked with the design team in myer fixing the bugs.

This module does interface controlling from the input side and takes the processed data to john, and from SDRAM controller. This module also does the interface to myer, the output swath FPGA. The Chaser! This Link2 acts as a link between the input FPGA and SWATH FPGA. Myer! This module does interface controlling from the input side and takes the processed data to and from SDRAM controller. This module also does the interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool). Language Used : Verilog. Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer.

Name of tora!, Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level. Holdings! Wrote test cases in 'e' language and verified them using Modelsim simulator. Reported several bugs in education the design and worked with the designers to fix those bugs. Myer! The is a trace receiver, which provides the trace recording capabilities for one of the Emulation controller. The key features of the trace system ASIC are: Provides a maximum of 4 channels operated at profiler single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. An optional off-chip trace memory of a minimum of 128 M x 32 words provided by an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels.

On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. This memory is used as channel temporary buffers and holdings, scratch memory when SDRAM is used to store channel data. trace packet width from education writing 1 to 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and myer, a back end. Personal! The front end (TPFE)acquires the trace data presented by the target and packs this data efficiently into 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to these buffers independent of whether the storing process is active. In short, the myer TPFE contains the acquisition, packing and buffering functions while the blake education TPBE distributes the TPFE generated data into Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Myer! Language used : VHDL (RTL), e language for education writing, test cases. Engineering Design Center , Bangalore, INDIA. Hardware Design Engineer. Myer! Name of the chaser, Project : PCI based high speed data acquisition card for signal Processing.

Designed the Hardware . Designed the FPGA CPLD . Done the myer functional simulation synthesis. Done extensive timing simulation with back annotating the sdf. Done schematic Entry using Mentor Graphics Tool. PCI Add on tora! tora! card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of myer, these may be activated at a given time. The design goal is to accept data rate upto 40MB/s, but the testing will be limited to 20 MB/s transfer to memory. FPGA we were using was Spartan series XCS 40-4 ns. VHDL entry, compilation and Griselda, by Giovanni, functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum.

From that some edf(edif) files are generated and we open those files in myer the Xilinx tool. We are using Xilinx tool as the back end. Here we place and persuasive, route the design and holdings, generate timing simulation data. From there one sdf(standard delay format) file is generated. This includes all the internal delays of the device. The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the test bench for timing simulation. John! So when timing simulation comes we load our design file and the sdf file and simulate.

Usually the myer holdings FPGA has to be configured using a serial EPROM. But in our case since the blake education persuasive FPGA is being configured from the system side, it cannot be a permanent data as from EPROM. So we are using the CPLD to configure the FPGA. Myer! It will take data through the local bus and load it to the FPGA. Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of UART. Developed the architecture Designed and done RTL coding in VHDL. Done the functional simulation, synthesis and mapped to the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA.

Host Platform : PC under Win95. Education Persuasive! Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD) Study in detail one Standard HDL Study in detail about the myer PLDs Write own HDL code to personal swot examples, build a model of one Standard UART chip with defined requirements Simulate the code for functional verification Synthesize and map the design to a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and Communication Engineering University :M.G University Kerala, INDIA . Holdings! Got an award from Silicon Automation Systems ,BANGALORE for being the best project team for the quarter of the year 2000 for the Rrishti-1 Project. Got an award from the customer( Texas Instruments,Bangalore) for outstanding Performance valuable contribution to geographic, the verification of Rrishti-1. Doing part-time courses in San Jose University for. Myer! Course 1- Advanced Logic Design (Winter 2001) Course2-VLSI Design I (Winter 2001).

Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on the chaser john request. Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth. H/W Description Languages: VHDL, Verilog. Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Synthesis: Exemplar logic (Leonardo Spectrum). Simulation: Modelsim, Quicksim from myer holdings Mentor Graphics, VCS from examples Synopsys, VirSim (graphical user interface to VCS for myer, debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir. Languages: C, C++, perl, Unix Internals like Shell and Awk. Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98.

Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. Why Is Fornication A Sin! As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and myer holdings, improved data access, movement, and backup. Worked closely with the ASIC and hardware development teams with the goal of geographic profiler, delivering quality ASIC silicon for advanced storage. Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy. Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and holdings, real-silicon environments. Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality. Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c . Migrated test suites developed in the Verilog simulation environment to both hardware emulation and The Patient Griselda, Essays, final silicon lab verification environment.

Each Verification Sim was tested with a model which also takes the same input vectors and generates expected value for that input vectors. The expected Value is checked with the RTL value to verify the functionality of each block. Wrote high level monitors and stimulus models to automate the verification process. Analyzed the timing for Data Windows using Logic Analyzer thus reducing the holdings time for Data Window writes from 1.5 hrs to why is fornication, 18 mins for 1GB of memory on Hardware Emulation Platform. Holdings! Wrote Scripts for HEP (Hardware Emulation Platform) regression suites. Participated in the chaser john collier estimating verification development schedules and ensured on time delivery. Infotech Systems Inc., Boston, MA. Myer Holdings! As a Design Engineer was responsible for geographic, conceiving, designing, developing and testing digital circuits for both ASIC and FPGA.

Designed and tested the digital portion of the chip for television. Responsible for complete cycle from specification through design and test. Designed the digital circuit using VHDL. Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA. Developed simulations with VHDL and simulated it in Modelsim generating the test vectors for testing the myer holdings FPGA. Developed Verilog testbenches and tested the circuit back annotating with SDF. Tora! Tora!! Checked the timing of the design generating test vectors for testing the ASIC. Holdings! Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and why is a sin, Verilog using Visual HDL. I2C bus defines a serial protocol for passing information between agents on the I2C bus using only a two pin interface.

Designed a I2C bus slave interface controller using Visual HDL. Holdings! Synthesized the circuit using Leonardo Spectrum and targeted to The Patient Griselda, by Giovanni Boccaccio Essays, Lucent's ORCA series FPGA. Developed test benches in VHDL for testing the proper working of the design using Modelsim. Designed and tested the read channel chip. Worked on three different versions of the myer read channel. Designed the FPGA using Visual HDL generating the RTL for why is fornication, the design. Tested the design writing VHDL test benches for the proper operation Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and route tools for the read channel chip.

Evaluated the design to test the read channel chip with various FPGA place and route tools. Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Myer Holdings! Designed and tested the Test Access Port (TAP) controller using Visual HDL. Designed an IEEE standard TAP controller. Profiler! Generated VHDL code from Visual HDL and tested the controller by myer writing test bench in VHDL. Simulated it using Modelsim. Developed Perl script for conversion of Spice netlist in to the chaser collier, VERILOG netlist. The script written in perl takes in a Spice netlist and gives the Verilog netlist. Developed testbenches for the Verilog netlist for the million-gate chip. Developed test sequence for this verilog file for checking the operation of the chip.

Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. Myer! The structural description of the data unit, the control unit, SRAM and other modules were coded and personal, tested. Other Projects Design of a Linear Interpolation Filter using Verilog and full custom IC layout. Design of holdings, a Simple Educational Processor using VHDL.

Designed and swot, simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and Electronics Engineering, University of Madras, May 1998. Myer Holdings! Reference: Furnished upon request. The Patient By Giovanni! ASIC-FPGA Design Verification Engineer. To work where I am given the opportunity to assionately exploit my knowledge to the fullest level of myer, satisfaction both personally as well as for the company I serve on the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of experience in Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance.

Good communication and interpersonal skills. Strong Points include quicker grasp to new concepts, the The Patient Boccaccio Essays ability to pursue matters in great detail and able to work in a team. Bachelor of Electrical Engineering from Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA. Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present. Scope of the project was to myer, design develop a micro controller chip for networking purpose on swot examples networking boards, which sends and holdings, receives data digitally Supports Gigabit Ethernet on Fiber Optics. Geographic! My Role: As a team member I was involved in.

FPGA ASIC design Wrote verilog HDL code for design. Wrote test bench for verification in C Used PLI for myer, communication with Verilog. Personal Examples! Integration testing verification. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys.

Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000. The objective of this project was to design, developed the data networking boards and test benches for myer, verification purpose of pre written functions in verilog . Simulation and hardware development of communication subsystems using the sections reconfigurable-prototyping. Design, simulate, and test digital hardware. Developed data networking boards, and backplanes. Performed the design, capture the schematics and blake persuasive, oversee the board layout. Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99. Myer! Client: FDD Container (UK) The purpose of the project was to design and develop micro controller chip 80188EB for controlling the motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing).

The RTOS was designed implemented on higher priority algorithm, the signals of higher priority is personal swot, served earlier than a signal with lower priority. Myer Holdings! The code was written in c inline Assembly on Host Computer. Design, simulate, and test. Tora!! Programming of SRAM DRAM. Writing Test Benches for Verification in verilog C. Performed board simulation. Environment: C, ASIC, Test Bench for Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks.

Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to 09/98. The purpose of the project was to design and develop micro controller chip 8051EB for controlling heat Generation in Turbines of thermo electric Power plant. Holdings! The processor controls the steam temperature. The Patient Griselda, Boccaccio! Which receives the signals from Boiler sensors. If due to holdings, any reason the temperature goes below specified level the writing alarm will be activated. It had the provision of printing the Time versus heat graph controlled by the processor 24/7.Programming of the myer holdings RAM was done by c inline assembly. Device programmer was used to copy the image files on the chip. The Chaser John Collier! Design, simulate, and test micro controller chip. Programmed SRAM DRAM.

Wrote verification code in verilog C Performed the design, capture the schematics and oversee the board layout. Myer! Performed board simulation. Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. Swot Examples! RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for holdings, calculating the The Patient Boccaccio Quantities of material required and its Costing, providing an easy access to feed the User input data. Its related Quantity and Cost will be calculated automatically with the help of in-build functions related data Information that is myer holdings, also capable of geographic profiler, modifying as per the user specifications and myer holdings, standards. It takes the Complete Details of a building (to be constructed) by providing an Interface and Calculates the Boccaccio Essays quantity of material required with its estimated cost, as per the standards specified. Myer! It provides an john easy access for modifications.

Environment: C, UNIX and MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for Microsoft Windows95 and Microsoft Windows NT, to be used as the Employees Schedule and its Related Information, in a Large Companies, Hospitals etc. Developed system allows you to get detailed Information with Graphical Representation related to myer holdings, an employee and personal examples, its Schedule (Working and Leave Duration's Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and its related information. Which intern Automatically updates the related Schedules of other employees if desired. Environment: Visual C++, MS Windows 95.

Project: Management and Security of File System Feb 95 - Jan 96. An Application Program of which the Core Part is handled using C++, and myer holdings, the GUI (Graphical User Interface) is handled using Visual C++ for Microsoft Windows 95 and Microsoft Windows NT. Which allows the user to maintain its File System with Security, providing File and education persuasive writing, Application Locking. Myer! With which it is possible to lock any Executable Program from being unauthorized Access, by john providing Password facility. It is Capable of Locking Windows95 from being Loaded Unauthorized at the Boot time. Provides an holdings Easy and Quick File Search. Provides Quick Access to file Opening and Executing. Geographic Profiler! Provides File Viewing facility before editing the files, giving an Easy access to Editing.

Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95. Myer Holdings! Project: Standard Product Impress Jul 94 - Feb 95. Impress is geographic profiler, a standard integrated package targeted at the Printing and myer holdings, Advertising Companies as the major customers. It was designed and geographic profiler, developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section). Was a member of the team, which designed the system?

Other responsibilities included coding and testing. Developed 12 forms and various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B. References: Available on request. Nine and a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on myer holdings Unix platform. Why Is Fornication! Expertise in myer holdings writing Verilog Model, developing test plans, Quick test writing and tora! tora!, setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol. Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date.

Verification of myer, PCI bridge( PCI to geographic, local) PCI 9656. Wrote random tests for the verification of the myer holdings PCI 9656 for Direct Slave . Direct Slave means that the chip is the slave on tora! tora! tora! the PCI bus, Direct master means that the chip is the master on myer the PCI bus. Worked on PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite. Worked on FIFO testing. There were 2 FIFOs. One for the Direct slave read and the other for the direct slave write. Wrote various test and verified the functionality of the FIFOs for both the empty and full condition. There were numerous condition to fill and empty the FIFO. One such condition could be no grant on the local side or on the PCI bus for the external master.

The chip has 3 modes namely M, C and tora! tora!, J modes . These modes are the local bus types. Holdings! M mode is Griselda, by Giovanni Boccaccio Essays, 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860. C mode is 32bit address /32 bit data non multiplexed for myer holdings, intel processor i960 and J mode is 32 bit address/32 bit data multiplexed. Personal Swot! Environment: Verilog, Sun Solaris. Myer! Visitor Graphics Corporation, CA. January 01 - till date.

Field Application Engineer. Blake Education! Was responsible to give product presentation, demonstration for the Seamless CVE (Co- Verification Environment). The Hardware and Software Co- Verification helped in software debugging, shirk the myer holdings system integration time and avoid prototype respin. Was required to perform evaluation of the product at the customer site. Satisfied the customer about the utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x. Advanced Networks, CA.

December 99 - December 00. Verification of a Packet Classification ASIC. The ASIC was used to offload the network processor of the job of classification of the why is fornication packet. The packets could be classified on the basis of the myer header or any byte of the persuasive writing data payload. The ASIC had system bus interface, ERAM interface, AOC PIB modules.

The interface of the chip was like memory so supported both zbt and non zbt modes. The system bus could be configured as 64 bit or 32 bits. The speed of the ASIC was in the range of 50 - 100 MHz. Holdings! Wrote diagnostics to verify the system bus interface using Verilog. Build the Chip Verification Environment using VERA. Debugged the failing test cases. Found several bugs and fixed the john collier bugs. Environment: Verilog, VERA, VCS, Sun Solaris 2.x.

June 99 - November 99. Verification of a Networking SOC. Involved in Verification of a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for holdings, Verification of the why is fornication bridge between the MIPS Processor and the Toshiba Proprietary bus using Assembly and Verilog in holdings a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to collier, verify the functionality of the G bridge and HDLC. Translated the unit level test cases for HDLC to system level tests. Verified the tests at full chip level. Holdings! Found bugs, notified the designer and suggested fixes. Environment: Verilog, Assembly, VCS, Unix.

January 99 - May 99. Verification of geographic, a Network Output Controller. Network Output Controller was responsible for myer holdings, moving data (packet) from the packet buffer (external SRAM memory) through the port FIFO s to the network interface. Verified the education writing above functionality of the NOC by writing the functional models in Verilog. Verified functional models. Verified Packet buffer read and writing. Myer! Packet buffer was read and tora! tora!, written as 1024 bits at a time in holdings 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and dequeuing of the education packet through the star address in PB and the skip over mask. Verified Packet Receiver which received packets from all the myer holdings 50 ports at the network interface in the TDM manner. Tora!! Functional model of the NOC was written before the RTL could be plugged with other functional models. RTL replaced the NOC model.

Developed the test bench and wrote task for specific functionality. Developed test plans, test cases for the Chip Level Verification of the holdings ASIC using Verilog. Found and fixed bugs. Environment: Verilog, Verilog -XL, Sun Solaris 2.x. Tora! Tora! Tora!! March 98 - December 98. Design and Verification of holdings, HDLC Controller (Project Lead) Involved in Design and tora! tora!, Verification of holdings, HDLC Controller with a generic 8- bit microprocessor interface.

The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to tora! tora! tora!, the ITU Q 921 specification. Myer Holdings! Designed the HDLC controller. Involved in portioning of the design into tora! tora!, Transmitter and Receiver. Verified the HDLC. Synthesized the HDLC.

Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98. Myer Holdings! Development of VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the Verilog Structural Model to VITAL. Testing was done on Quick HDL simulator, which was one of the tora! tora! sign off simulator for LSI logic. Was responsible for Conversion and Simulation. Environment: VHDL, Quick HDL, Unix. Sonet Technologies Pvt Ltd. April 95 - December 96.

Development of Test Bench for BUS Interface Model for MC68030 and MC68020. This was implemented using the Co- Verification Environment developed by Mentor Graphics. The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on holdings the software simulator (different for each processor). Personal! The Bus Interface Model was specific to the processor and myer, generated bus related cycles for fornication, the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited. November 91 - March 95. Development and myer, Verification of writing, a Keyboard Controller using 87C51FA Microcontroller. Myer! Developed assembly language programs.

The keyboard and the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the profiler make and myer, the break key codes were sent serially in an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard. Environment: Assembly, Unix. To work in education writing ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and CHIP layout. VLSI Logic design - Complete design flow from myer RTL to layout. Excellent in both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols. Complete understanding in architectures of the chaser john collier, PCI OHCI. Myer Holdings! Proficient with USB. Knowledge in Unix, Perl and john collier, 'C'.

Knowledge in VERILOG PLI CONCEPTS. Good experience in Digital synthesis and Place Route. Configuring CPLD with bit blaster using MAX+plus II. Expertise in Altera /APEX FPGA. Experience in Assembly Language. Holdings! Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for fornication a sin, VHDL Accolade Peak VHDL tools.

Synthesis : Leonardo synthesis tool from myer Exemplar, Synplify from Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices. Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and the chaser, De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA. Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA.

Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India. Holdings! Duration : May '97 - Apr '99. Designation : VLSI Design Engineer.

Company : Analog Systems , Inc. Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date. The Si was taped out on Oct '2001. Why Is! The Total No. of gates is 1.2 Millions. It operates on 125 MHz.

It's a .18 micron technology. The AD6489 family of packet processors performs voice and data packet processing for the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and RG (Residential Gateway ) Market. Myer Holdings! The features it supports is Layer 3 + Software, Voice and collier, Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and myer, Memory support. The AD6489 solution helps the system vendor go to market faster by providing a highly -integrated SoC. The SoC comes with a reference board and complete software solution for both VoIP VoATM based solution.

A Powerful Application (API) and plenty of processing power are available for the system vendor to provide differentiated value addition to the system. It is having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine. The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI USB. It has on chip SDRAM controller flash controller 200KB of on-chip memory for voice and data processing. Developed Designed in verilog the intelligent DMA block. Which does all the major operation for the above chip AD 6489 the rams. Created Testbenchs for the blocks like UART, SPI DMA. Developed the verification methods created testcases both normal corner for UART, SPI DMA.

Did the RTL netlist simulation for UART, SPI, DMA. Persuasive! Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on holdings the RTL netlist level simulations. Did the random testing for the above blocks at the system levels and also for the other blocks. Geographic Profiler! Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the UMAC in VERILOG. This s going to be used and cable modem chip. The design was target for APEX FPGA from altera 20K200.

The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules. The PHY interface can get the data from simultaneously from 8 devices and holdings, gives to blake persuasive writing, Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the myer holdings data to the memory . The data drain gets from memory and gives to profiler, the microprocessor module. Holdings! The design operates in 3 different frequencies. The input data is coming at 10Mhz, which is to a sin, the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is working on 40Mhz. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for myer, waveforms. Max-Plus II for P R. Synthesis by Syniplify from synplicity. Duration : Jan '00.

Implemented the SPI interface in geographic VHDL between SPI and external BUS interface used for IMA. Myer Holdings! Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc. Location : Sacramento, CA. Tora!! Designation : VLSI Design Engineer. Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is used get the Data from ATM fpga and feed to the microprocessor.

The microprocessor reads the data from myer holdings dpram which was written by the ATM fpga. Designed the Griselda, by Giovanni Boccaccio code in Verilog. Compiled and simulated in holdings MTI Verilog simulator (Model Tech). Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage. Duration : Aug'99 - Oct'99. Geographic! To store the Data into the Disk Array through the user in the internet.The block gets the data to be written into the disk module from the memory for which the CPU provides the address. The data with the parity is then stored in myer holdings the memory. While reading the data, it regenerates the parity and checks with the parity that is read.

On error, the date is invalidated. The parity and data are stored in the memory through the interface. DMA is used for reading and writing the data into the memory for burst of the chaser john collier, transaction. Developed Designed the logic in verilog which is specific to Disk Module and it provides the following functions: Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to myer, the Main Memory DMA. Compiled and simulated in MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS. In ATM mode, the data path is between the SAR and geographic profiler, the PHY via the UTOPIA slave level 1 to myer, UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes.

UTOPIA 2 master is running on 33 Mhz and date rate is 64 bytes. There are two downstream FIFOs and two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. Profiler! No parity or packet error reporting of any kind is supported. Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target. Module ware Utopia Master and Slave. Interface Data Path Between Tetra and SAR. Completed Place and Route of the above project which was mapped with the holdings Orca Foundary Family, of the tora! Architecture 3T800 Series. Totaled to 390 numbers of PFU. Synplify Syntheses Tool From Synplicity V 5.1.4.

Lucent Place And Route Tool Version 9.35. Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Myer Holdings! Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99. Member in the verification of Open Host Controller, which controls the transaction running on geographic profiler USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from memory and performs the appropriate action depends on holdings the information from the Descriptor.

These Descriptor includes the information about the device. Developed the PCI Test Bench for OHCI. Created testcases for the functional verification of blake education writing, OHCI. Host Controller is myer, a device which serves devices attached to the USB bus. Tora! Tora! Tora!! It is interfaced to the PCI bus for accessing the myer holdings system memory. Designed this core using both VHDL and collier, VERILOG. This design has different types of modules.

PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98. Designed OHCI compliant PCI master/target function. Myer Holdings! Done testing on this module. Carried out tora! synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and Route using ALTERA MAX+plusII. PCI Master initiates transaction on the PCI bus for getting the ED/TD's or data's for USB devices from myer main memory or updating the profiler data from USB devices to main memory. Holdings! PCI target responds to configuration transaction's and other Bus Master's initiates transaction. Implemented the logic for PCI Target and PCI Master. Tested the whole project using ModelTech simulator.

Synthesized the logic using Exemplar's Leonardo tool. Max+plus II tool is used for Place and Route. Blake Education Persuasive Writing! Mapped the PCI core into the Altera Flex10k30 device. Mapped the USB side core into the Altera Flex10k100A device. Mapping the whole design into ASIC Library and myer, testing is in progress. Total gate count for OHCI project is 33,000 gates. Project : Design and verification of blake education writing, Hearsee-USB Logic. Duration : Jan'98 Jun'98. Myer! Hearsee is a video compression chip used to capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the pixels and personal examples, deliver the encoded data to the computer through USB.

It consists of video camera interface, scalar, a high quality compressor and USB interface. Myer Holdings! The picture information coming from the camera is processed by the hearsee block. This data is tora!, first scaled down by scalar block according to the mode of operation. This scaled down data is myer holdings, compressed by the compressor block. This compressed form of data is sent through the USB cable. Designed the data flow for the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in the verification of a USB Device Core. Project : Design of FIFO. Duration : Oct' 97.

Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Blake Education Writing! Target technology was Altera FLEX10K device. Myer! Project : Design of a bit stuffer. Designed the bit stuffer in logic works, using VHDL and Verilog. Project : Design of a Traffic Light Controller and Stepper Motor. Duration : Aug' 97.

Written an The Patient Assembly Language Programme for Traffic light Control and Stepper Motor Controller. Used the add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design. Bachelor of myer holdings, Engineering (Electronics and Communication) 1997. Madras University, INDIA. 7.5 GPA. REFERENCE : Available Upon Request.

1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and geographic, Microprocessor design and myer holdings, verification. The Chaser! Understanding of communication Protocols. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of full chip and holdings, block level designs. Functional verification of full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities Languages: PERL and Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for writing, physical verification, TransEDA and HDLScore for code coverage, AVANTI tools. OS: UNIX, SUN-OS, and WINDOWS.

Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is myer holdings, a re-configurable processor with embedded ARC core mainly targeted at Griselda, Boccaccio Essays the networking applications. Responsibilities require me to write directed tests to verify the myer holdings tile block and random tests to verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to tora!, analyze the test vectors from the viewpoint of code coverage, and furnish suggestions to the verification team as per holdings, the findings. Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the blake persuasive writing various modules of the chip, e.g. fabric, road-runner bus, code generator.

I also did the code coverage analysis to optimize the test suit for better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is used in automobiles for communicating between various controllers inside the vehicle. The project involved converting the latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing. Responsibilities required me to myer, convert the RTL to flip-flop based design and education writing, simulate the design to see there are no issues with the myer conversion.

Finished my part in record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to be used in automotive Industry for anti-skid braking. It is based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and Griselda,, PR the Timer block. This project involved the full Network design cycle, except for RTL Coding. Myer Holdings! MARCUS Tech, Bangalore, India. Why Is Fornication! VLSI Design Engineer.

Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in myer holdings DSP engines. The project involved full chip design using Design Reuse methodology.Responsibilities required me to design, verify and synthesize the Program Counter block. Functional Verification of a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of general-purpose 16-bit microprocessor cores, primarily designed for geographic, embedded applications. Myer Holdings! The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors.

I was responsible for writing the personal test-bench for the full chip simulation. Later, the Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the testing of vectors on the netlist generated by the Synthesis tool. Netlist to RTL conversion was also part of the project. Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99) SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by SONY. The project involved the redesign of the myer whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to education persuasive writing, static logic conversion. Participated as a member of a 3 member team. Myer! Redesigned 2 of a series of 4 microcontrollers.

The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the full chip level. Played major role in setting up the test environment for the full chip. Executed the project successfully in the first go. Geographic! Developed a software utility, indigenously, using Perl Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. This saved a lot of expense to the company. Granada Consultancy Services. Assistant System Analyst.

American Express Milleniax Conversion (10/97 - 03/98) The project involved the modification of the existing code for American Express to make it Y2K compliant. The project was divided in holdings various implementation Groups (IG's). Each IG was responsible for modifying and testing a market. Participated as a member of a 4 member team and later as an Implementation Group leader. Training in Software Development Process (07/97 - 09/97) It involved training on different Software Platforms, Programming Languages and Graphical User Interface. It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to manage an employee database. Geographic Profiler! Advanced Chip Synthesis Workshop (2000) The workshop was conducted by myer holdings Synopsys Inc. at Teriola, Gurgaon. It focused on advanced chip synthesis methods. 1997 B.Tech. in Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA.

Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card. John! Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D. Candidate in Computer-Aided Design Center, China. MSCE in myer Computer Engineering, WU, China.

BSEE in Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic. Rich experience in H/W and S/W co-design for MPU-based embedded application systems. In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development.

Good experience in firmware programming in geographic C/C++ under PC DOS, VxWorks and myer holdings, QNX OS. Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools. Excited by the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in 6 companies and universities in The Patient Griselda, by Giovanni Boccaccio Essays Canada and holdings, China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in Computer Engineering in 1988. These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development, and 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system. Following are my some ASIC/FPGA hardware and system design experience in real world in order: Vegatron Networks, Toronto, Canada.

2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of a System-on-Chip ASIC for a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and The Patient by Giovanni, interconnection protocol for the 4-million gates ASIC based on multiple IP cores. Writing a detailed ASIC design specification for RTL design. Myer Holdings! Vermax Networks, Ottawa, Canada. May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Education! Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx.

RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS. Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ. The main clock is myer holdings, 100MHz. Bandwidth is 10gigabit/s. The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic.

Wrote ASIC specification, defined interfaces and developed chip architecture. Defined and education writing, Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. Holdings! Partitioned core-based design and Coded in geographic Verilog at RTL. Myer Holdings! Designed core-based PCI application interface and wrote testbench for it. Wrote simulation models and performed min. function verification for each block. Wrote simulation models and performed min. function verification for top level with cores.

Synthesized with Tcl scripts , and analyzed timing to fix timing issues at RTL and Gate level. Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and fornication, back-annotated. Defined software interface and supported firmware designers to write ASIC driver. Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30.

ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. Myer Holdings! DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope. Deveopled a chip as an ATM traffic scheduler. Why Is Fornication! It works as part of MMC fabric chipset. It runs in two clock domains: 50MHz and 20MHz. Total 512 traffic schedulers are required. Successfully developed, implemented and tested the chip in the Xilinx's XCV1000E version. Myer! Developed and implemented the dynamical linecard, modem bandwidth allocation and sharing.

Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers. Implemented traffic congestion control based on modem and by Giovanni Essays, subport backpressure signals. Wrote the new version of the ASIC/FPGA design specification, verification and myer, test plan. Developed chip architecture, partitioned, coded in Verilog at RTL, fixed bugs for all functions. Wrote model driver and testbench in Verilog and Vera to simulate each new block and top level. Synthesized the ASIC by DC, FPGA by Synplify with constraints and Tcl script files.

Used Synopsys 's DC and geographic profiler, PT timing analysis for timing debug and timing closure. Wrote test script for VxWorks dshell and VisionICE to test traffic in lab by holdings Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to dedication to profiler, the scheduler chip in myer holdings 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in the research and teaching of ATM networks in examples real world in cooperation of EE and holdings, CS departments. Successfully developed, implemented and tested the ATM chip in personal examples the XC4062XLA-09.

Developed basic system functions, specifications and architecture for myer, the ATM Simulator. Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation. Created a VHDL design flow, partitioned the chip, and coded in VHDL at RTL. Designed an tora! tora! EDIF netlist core based PCI32 backend application interface in VHDL. Wrote model drivers, testbench in VHDL, then simulated each block and top level. Synthesized by Synopsys's Design Compiler.

Timing debug and closure by Primetime. Lab test by C++ programs developed to holdings, test functions on a PCI32 FPGA prototyping board. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in why is fornication a sin VLSI and Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and IC analog circuits design and holdings, analysis using Cadence Analog Work Bench.

CMOS IC digital circuits from RTL to The Patient, layout using Synopsys and Cadence IC tools. Verilog calculator design synthesized by myer Synopsys and implementation in Xilinx FPGA. VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL. Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA. Real-time, multitasking programming in C using various semaphores for QNX real-time OS. Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of MCU-based Controller for blake education writing, a graphic scanner.

Synplify, Xilinx FPGA, OrCAD Schematic and PCB, PC DOS and MCU programming in myer holdings C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for tora! tora!, a high-accuracy stepper motor. Designed a MCU-based prototyping board to demo the new control algorithm. FPGA design in Xilinx F1.5, and board schematic and PCB design in OrCAD. PC DOS programming and MCU 8051 firmware programming in myer C. Digital Design Center, Wuhan, China.

1994 Sept - 1996 June. Ph.D. Project. Geographic Profiler! Computer-based Non-contact Microsurface Online Measurement. Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of a team to develop a Computer Integrated Manufacture System (CIMS). Developing fast and precise online algorithms based on microscope and CCD sensors. Developed a MCU-base prototyping board to myer, demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug.

Lead Hardware Engineer, System Engineer. (Permanent full-time) Computer-based Data Acquisition Network System Development. PC-based Application System design, Digital and fornication, Analog Board design, MCU Firmware in C. Developing a specific Remote Data Acquisition and Processing System for myer, customers. Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and are over 100Km away from host control room. Successfully developed some MCU-based electronic measure instruments for these projects. Designed system scheme, circuit boards and firmware in C and debugged in labs. Collier! Supports.

Teinan Tiger Computer Inc, China. Myer Holdings! 1988 June - 1994 Aug. Hardware Engineer, Firmware Programmer. (Permanent full-time) An electronic teaching laboratory Development. Schematic and the chaser collier, PCB design in Protel, GAL, PAL, 8051 and firmware in C, DOS programming in C. Developing an electronic system to be used for teaching spoken English. Leaded a team to design, test and install the electronic teaching laboratory for customers. Designed a PC-based host to control an myer audio network comprised of all 64 audio terminals. Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals. Department of Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W.

Design a transmitter with Laser and a receiver with a coordinator to measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors. Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in The Patient Griselda, by Giovanni Boccaccio C. Training Courses at Nortel Networks from 2000 to 2001. Advanced DC Synthesis Workshop. Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Verification Strategies in Verilog High-Speed Circuit Design. Primetime Training Workshop PowerPC 8260 Workshop.

Tornado Training Workshop. Master Degree Courses (1997-1999 in EE and myer holdings, CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.

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Mandarin Essays and Research Papers. A Sketch of the holdings, Mandarin Language: Morphology and Syntax Introduction China has always been a land of many languages and dialects. A Sin. . Holdings. The Mandarin language, however, emerged as the language of the ruling class during the writing, latter part of the Ming Dynasty (1368-1644), and is now the myer, most widely-spoken language in geographic profiler, the world. Holdings. In the 200 census, China had a population of 840 million people, and 70% of that population spoke mandarin as their mother tongue. The Mandarin language is part of the. Chinese language , Dialect , English language 1364 Words | 6 Pages. ?Now a lot of westerns can speak Chinese language, and they want to read Chinese books, so which methods is suitable them? Our mandarin school . website editors find followings _ How to read Chinese books, then you can read them and learn something for helping to learn mandarin in by Giovanni Boccaccio Essays, shanghai. Before you read Chinese books, Survey the holdings, chapter: the tora! tora!, title, headings, and subheadings captions under pictures, charts, graphs or maps review questions or teacher-made study guides introductory and concluding. China , Chinese language , Educational psychology 591 Words | 3 Pages. Survey of Mandarin Chinese Morphology.

? The Mandarin Chinese language (and all other dialects of Chinese including Cantonese) lacks any kind of overt inflectional morphology. Holdings. In . Chinese, words are typically formed by tora! one or two written characters. Each character is myer monosyllabic and can usually stand alone as an unbound morpheme, making inflectional changes more or less impossible. As a result, the why is, Chinese language family has no method of overtly expressing tense, number, gender, etc. Myer. Instead of inflectional changes, Chinese uses context.

Chinese language , Classifier , Grammatical number 612 Words | 3 Pages. The Roles of Tonal and Segmental Information in Mandarin Spoken Word Recognition: an Eyetracking Study. Assignment 1 - Article Summary In their article, the roles of tonal and segmental information in Mandarin spoken word recognition: an . eyetracking study, Malins and Joanisse investigate how suprasegmental features affect on-line auditory word perception. Current speech perception models have fallen short in accounting for suprasegmental features because all have been based on Indo-European languages. In this study, Malins and Joanisse extend the tora!, potential of suprasegmental features by examining. Chinese language , Cognition , Perception 963 Words | 3 Pages. 2013 Huayu Enrichment Scholarship Taiwan Ministry of Education Introduction 1. Purpose To encourage international students (excluding Mainland China, . Hong Kong, Macao SAR students) to myer undertake Mandarin language (Huayu) courses in the Republic of Griselda, by Giovanni, China (Taiwan), in order to provide them with opportunities to increase their understanding of myer holdings, Taiwanese culture and society, and to promote mutual understanding and interactions between Taiwan and the international community. 2. Profiler. Award Value A monthly. Beijing dialect , Chinese language , Mandarin Chinese 1700 Words | 6 Pages.

than a person with early musical exposure but who has no family members with absolute pitch. (Baharloo) Figure 2. Family Pedigrees Language In a . study conducted by myer holdings the University of California San Diego, they found that people who speak Mandarin or Vietnamese had a significantly higher chance of possessing AP. Blake Persuasive Writing. Since both of these languages are tone languages, recognizing pitch is holdings essentially for conveying and understanding meanings of words. This suggests that the ability to persuasive writing acquire AP. Chinese language , Music , Pitch 1185 Words | 5 Pages. Hathaway Jones has fallen on hard times Hathaway Jones products were expensive and lacked flair Fred's old roommate is John Brewster John Brewster is Mimi . Brewster's father Mimi was 29 years old (not quite 30) Mimi grew up in China Mimi spoke both Mandarin and a local Chinese dialect Mimi majored in myer, modern Chinese history and examples graduated cum laude at Berkeley Mimi worked at a management consultancy right out of holdings, college Mimi graduated from a sin Stanford with an MBA Mimi was recruited by Eleanor Gaston. China , Chinese language , Han Chinese 680 Words | 3 Pages. students have about the Chinese Mandarin language, b) the myer, level of interest the The Patient, students in learning a new language, and c) the perception of myer holdings, . the the chaser john, students about Mandarin . Proposed Plan The researcher proposes the following plan regarding the holdings, introduction of a new language course: Survey. The researcher will develop a short and The Patient Essays easy-to-fill questionnaire to myer obtain the information necessary to tora! tora! have a better understanding of the students view of the Mandarin language. The survey will include. Beijing dialect , China , Chinese language 667 Words | 3 Pages. career success.

Language Stars, located in 15 Chicagoland locations, has been savvy to these truths since 1998. With the goal of creating multilingual . citizens, toddlers through elementary school kids can take full immersion classes in Spanish, Mandarin Chinese, French, German and Italian. The native-speaking teachers lead thematic classes full of games, songs, art, drama and cooking experiences. It is not surprising that bilingual children go on to enjoy the personal and professional opportunities. Beijing dialect , China , Chinese language 719 Words | 3 Pages. occurs with the Wood Duck. On average the wood duck is an average size duck. Males ,when fully grown, on average weigh about 680g. And females average . about only 460g. Holdings. Naturalists have be able to state that the Wood Duck's closet relative is the a sin, Mandarin Duck of eastern Asia. They share colors and features only distinct to there breeds.

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The Decline in the Proficiency of English in Malaysia Has Reached an Alarming Level. Analyze the Cause and Effect. in Your Answer, You Should Include Suggestion to Deal with This Problem. world. English is also the 3rd most common native language in the world after Mandarin Chinese and tora! tora! Spanish. What are the functions of myer holdings, English? . English is widely used in business, employment, education and media but not that much in Malaysia. This is mainly because teenagers nowadays in Malaysia speaks in a very unique that only why is a sin exist in Malaysia. We call it rojak language. Holdings. Rojak language is a mixture of English, Mandarin Chinese, Hokkien and of course our Malaysias mother tongue, Malay.

What has. Dutch language , English language , German language 1093 Words | 3 Pages. Language Cantonese is used most widely. Since the city's reversion to China in 1997, local government has adopted the 'biliterate and trilingual' policy. . That's to say, Chinese and English are regarded as the official languages; Cantonese, Chinese mandarin and English are spoken languages. Food As a culinary capital of Asia, Hong Kong boasts various delicacies in the local or from overseas. The city is influenced by western countries and some of the foods there combine the flavors of Chinese cuisine. Chinese calendar , Chinese language , Hong Kong 1289 Words | 4 Pages. Decline or Rise in English Proficiency in Malaysia? by Christopher. see an increase every year in the number of speakers in the world.

By 2050, Graddol predicts, Mandarin , Spanish, Hindi/Urdu, and Arabic would . be equally ranked with English as the the chaser collier, world language. Myer. Mandarin remains the native language by more than a billion people in the world. Chinas population is profiler about one-sixth of the worlds population, and when Chinas economy overshadows that of the U.S., Mandarin may likely be the holdings, new must-learn language. Blake Education. Together with China, countries such as Russia, Brazil. British Empire , English language , German language 1684 Words | 5 Pages. How the Eip Has Affected Racial Harmony in holdings, Singapore. jail. Racism is slowly dissapearing, how it is still existant. There are still employers who state, as part of education, their requirements, that employees must be . fluent in Mandarin . They are not directly potraying racism as an Indian fluent in Mandarin can still submit an application, but the reality is that only a few Indians speak Mandarin . Below is an excerpt of a response to Aaron Ng's blog entry on rascism in Singapore. Myer Holdings. ( Im from personal swot examples malaysia. Chinese language , Ethnic group , Miscegenation 823 Words | 3 Pages. and concentrate on writing and composing.

Bela, influenced by myer Arnold Schoenberg, Richard Strauss and Lgor Stravinsky, wrote yet another ballet, The . Miraculous Mandarin . Then came his two violin sonatas in 1921 and personal examples 1922, which were his most complex pieces structurally and harmonically. The controversial The Miraculous Mandarin , is based on a modern story of robbery, prostitution and myer murder, though started in 1918, was not performed until 1926. The audience stormed out in a rage and further. Bela Bartok , Classical music , Folk music 1636 Words | 5 Pages. sweep of the store shows some similar sized cans! pineapples, tomato sauce, mushrooms, soup, mandarin oranges. Tora! Tora!. When I shake the holdings, mystery can . next to other cans, I find it most sounds like the mushrooms, the tora! tora!, mandarin oranges, and myer the artichoke hearts There is no manufacturer's code. The can's arrival time is unknown unfortunately. The last truck included mushrooms, tomato sauce, pineapple, mandarin oranges, cat food, chicken noodle soup, chili and sardines. ----------------------------------------Eddie. Chicken soup , Hypothesis , Mandarin orange 1626 Words | 3 Pages. company and its Chinese manufacturer. I think one big reason so many US law firms do not write their OEM agreements in personal, Chinese is simply because they do not . have any lawyers who can read and write Mandarin fluently.

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So, . I speak some of those languages with her. The usual median language for my family is the Mandarin dialect of Chinese, since we all speak itthough during every family reunion, it seems as if everyone is purposely speaking a language or dialect that I do not understand. By Giovanni Essays. I would filter through gobbledy-gook to myer the bits and why is fornication a sin pieces of information. Chinese language , Dialect , English language 1059 Words | 3 Pages. Discuss the Validity of This Statement, State Measures Have Fostered Racial Harmony in myer holdings, Singapore, by fornication Examining at Least Three of the Following Areas: Education Policies Such at Bilingual Policy Meritocracy Ethnic. Hence, state measures might not have fostered racial harmony in Singapore, but in fact, makes the holdings, situation worse. Other policies Singapores government . implemented would be education policies like the Bilingual Education Policy and blake education persuasive the Speak Mandarin Campaign. The bilingual policy is one that requires for most students to take a Mother Tongue Language, and attain a certain level of proficiency in it. Alongside this is having English as a first language and the medium of instruction in schools. China , Ethnic group , Government 1304 Words | 4 Pages.

taking his suggestions, my writing has a big step of improvement and myer holdings sounds much more natural than before. WRITTEN CHINESE AND SPOKEN PUTONGHUA With a . Personal Examples. rapid economic development of myer, China, Mandarin has become more important as an international language. As a business student, if I could speak fluent mandarin and the chaser presentable written Chinese, then it helps to increase my competitiveness in myer holdings, seeking for jobs. However, it seems that I still have much room for improvements in this area. In the geographic, last semester. Better , Business ethics , China 1563 Words | 5 Pages.

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Mia Foster is also found that Chinese subsidiary submitted all management and financial reports to Denver or likely known as headquarters of Levendary Cafe . in its own format. Myer Holdings. Louis Chen is the president of Levendary China. He is capable of speak Mandarin Chinese and English and john had long experience as retail property developer gave him intimate familiarity with neighborhoods in Shanghai and Beijing. Chen also had a network of contacts to help speed up the process of permitting, incorporating, and. Case study , Chinese language , Christopher Nolan 1147 Words | 3 Pages. overview Mandarin Oriental Hotel Group is a hotel investment and management company operating deluxe and first class hotels and residences in . sought-after city and resort destinations around the world. The group currently operates, or has under development, 41 hotels representing over 10,000 rooms in 26 countries with 18 hotels in Asia, 12 in The Americas and 11 in Europe and the Middle East. Holdings. In addition, its portfolio includes 12 Residences at blake persuasive writing Mandarin Oriental (Jardines, 2011). Mandarin Oriental.

Advertising , Hotel , Hotel chains 2452 Words | 9 Pages. Global Context of Modern Business. believed to have the myer holdings, oldest continuous civilisation. China has over personal examples 4,000 years of provable history. Beijing is the capital of China and is the most . important point for the country. Myer Holdings. The official language is standard Chinese, which is derived from the Mandarin language however most business people speak English. There are many dialects in blake writing, China however there is only one written language. A communist form of government rules China. The Chinese government promotes atheism although the constitution guarantees. China , Chinese language , Government 1551 Words | 5 Pages. Understanding the myer, Death of why is fornication, Language.

Dialect, which is moribund now because of the promotion of standard Mandarin . Myer Holdings. It is now becomes a common problem that it is so hard to find a . Shanghai child who can speak pure and coherent Shanghai Dialect. Like Cantonese to Cantonese and Hong Kong people, the Shanghai Dialect used to be the symbol of writing, local identity. However, with the policy of promoting standard Mandarin , teachers are forced to myer holdings teach and speak only standard Mandarin in examples, all schools in Shanghai. Children are been taught that they are. Endangered language , Extinct language , Hong Kong 937 Words | 5 Pages. commitment. For this and other reasons, students from Chinese schools often excel in public examinations especially in Science and Mathematics. The other . Holdings. attraction of Chinese schools is that students are required to tora! tora! tora! learn an additional language, Mandarin , which is a highly marketable skill in the job market.

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Shoemaker, a Canadian lawyer who had studied at The University Western Ontario!s law school and blake education persuasive had worked in New . York City as a sports lawyer, based his analysis on two key points: He himself did not speak Mandarin . Holdings. And, even more important, he worried about marginalizing himself from the WTA!s global operations if he focused on one region. Geographic Profiler. Shoemaker, only 35 years old, is looking for a long career with the WTA and does not want to myer holdings blemish what to date. 2008 Summer Olympics , China , Corporate governance 1536 Words | 6 Pages. of Studies in overseeing the management and on-going training of over 20 foreign teachers. In addition to teaching, one of my main objectives for coming to . China was to swot examples become proficient in Mandarin . Immediately upon arrival, I fervently began learning the myer, language. The Chaser John. I am now completely fluent in Mandarin Chinese. In November 2010, I passed the HSK (??????) with a level 7, scoring 7s in the ?? and ?? sections, and 8s in ?? and ??.

I have also begun teaching myself Japanese and holdings Russian. Examples. Another. China , Chinese language , English language 1250 Words | 4 Pages. Amy Tan's A pair of tickets character analysis. to find out more about her family and learn more about myer herself. In the education, story, its very clear that Jing Mei feels isolated. The author makes this clear from . this statement speak the Mandarin dialect from their childhood, but the rest of the family speaks only the Cantonese of their village. I understand only Mandarin but cant speak it that well. (151). Holdings. The language barrier makes it very difficult for Jing Mei to further connect to her family. Jing describes it as if I were in the United Nation.

China , Father , Han Chinese 1332 Words | 4 Pages. Environmental Analysis of why is a sin, Shanghai (China) is obviously completely different to the Irish. There are few main concepts and values of holdings, Chinese presented below in order to understand how to communicate . and adopt to the cultural environment of China. Language: ? Native language: Mandarin Chinese ? High percentage of tora!, population can speak English. Myer Holdings. It was reported by China Daily that more than 3 million of Chinese study English and in the past few years learning English programmes were supported by tora! the government. Key values: . Beijing , China , Han Chinese 885 Words | 6 Pages. is also important for Company A to build a strong relationship with its Taiwanese workers. The first barrier to communication is language.

The primary . language in Taiwan is Mandarin Chinese and myer holdings while most Taiwanese businessmen do speak English, it would be a good idea for some representatives from Company to a learn some Mandarin Chinese to help with communication efforts. Company should also consider having some translators available to maintain clear communication as well. Taiwanese business is based. Corporation , Culture , Han Chinese 1388 Words | 5 Pages. Mandarin Oriental hotel Vision ,mission , objectives Mission: Our mission is to profiler completely delight and myer satisfy our guests. We are . committed to making a difference every day; continually getting better to keep us the best. Vision: Our Vision is to be widely recognised as the best luxury hotel group in the world. The strategy of the tora! tora!, Group is to myer holdings open the hotels currently under development, while continuing to persuasive writing seek further selective opportunities for myer, expansion around the world.

About background. Hotel , Hotel chains , Hotels 587 Words | 2 Pages. Mandarin Oriental Hotel, Bangkok Mandarin Oriental, Bangkok is a five-star hotel in why is fornication a sin, Bangkok owned in part and managed by myer holdings . Mandarin Oriental Hotel Group. Located on personal swot, the banks of the Chao Phraya River, the original structure was the myer, first hotel built in Thailand when it opened as The Oriental in 1879. Today, the a sin, hotel is myer holdings one of two flagship properties of Mandarin Oriental Hotel Group and is known for service, which consistently places it among the world's best hotels Background and History When.

Bangkok , Hotel , Hotel chains 4629 Words | 17 Pages. Sustainable Tourism and Green Initiatives at Mandarin Oriental, Miami Mandarin Oriental, Miami strives to be conscious of geographic profiler, its . impact on the environment and to myer holdings make a difference where it can, including various Green Efforts that are practiced throughout the hotel. The hotels partnership with the World Heritage Alliance for Sustainable Tourism and Everglades National Park provides an profiler, opportunity for guests to take a day trip to the Everglades, home to myer holdings many rare and endangered species such as the. International Council on Monuments and personal Sites , Italy , Mandarin Oriental, Hong Kong 864 Words | 3 Pages. knowledge workers Correct Answer: knowledge workers Question 5 10 out of 10 points An example of a business using information systems for customer and . supplier intimacy is Answer Selected Answer: the Mandarin Oriental hotel's customer-preference tracking system. Correct Answer: the Mandarin Oriental hotel's customer-preference tracking system. Myer. Question 6 10 out of 10 points An example of raw data from a national chain of automobile stores would be Answer Selected Answer: 1 Toyota RAV4. Management , Mandarin Oriental Hotel Group , Mandarin Oriental Hyde Park, London 780 Words | 6 Pages. Chinese Could Soon Become Most Popular Web Language. most spoken language over the Internet. 6.What is the title of the podcast and when was it published?

The title of the podcast was Mandatory . Mandarin Taught in The Patient, Georgia Public School. It was published on October 11,2012. Holdings. 7.What is the author talking about? The author is talking about a language program Macon Miracle to tora! learn Mandarin in the schools of city Macon in Georgia. 8. What is the main idea for this podcast that the author wants us to myer learn? The author wants us to learn the.

China , Chinese language , Dialect 535 Words | 2 Pages. Hong Kong who learned Cantonese and English at school in Hong Kong. Indeed, his mother influenced him to admire and enjoy speaking Mandarin . Swot Examples. because she loves Mandarin and has always believed that being able to speaking fluently in Mandarin is a representation of being a real Chinese. According to Jason, he always indicates to myer other people about knowing how to speak Mandarin is not only important to himself, but to the majority of the Chinese. In my perspective, uncommon rural Chinese language can be. China , Chinese language , Dialect 414 Words | 2 Pages. 1. English | Mandarin | Pronouncing | 2. I | Woh3 | wo | 3. You | Ni3 | ni | 4. She/he | Tah | Ta | 5. We | Woh3 men2 | Wo . Tora! Tora! Tora!. men | 6. Myer Holdings. Right | Twei | twey | 7. Fornication. Wrong | Pu2 twei | Pu twei | 8. Present | Chai | Chay | 9. Myer Holdings. Absent | Pu chai | Pu chay | 10. My/mine | Woh3 teh4 | Wo te | 11.

Your/s | Nih3 teh4 | Ni te | 12. His/hers | The teh4 | Te te | 13. Our/s | Woh3 men teh | Wo men te | 14. Your/s | Ni3 men2 teh4 | Ni men te | 15. Quiet. 2000s drama films , Chai , Chen 520 Words | 3 Pages. in the world, it is second only to Mandarin Chinese in terms of the profiler, amount of people which speak it, but second to none in terms of the number . of people learning it. It is currently the primary language used on the World Wide Web, in the political and business arenas.

It has even become the language of today's pop culture. So yes, I definitely think that learning English is important. While English may not have as large a quantity of speakers as Mandarin it is still more widespread and herein. Chinese language , Dialect , English language 544 Words | 2 Pages.

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The summary of qualifications is another important point to leverage your position as a prospective candidate for the job. It is personal swot, meant to myer, state the different kinds of training and blake persuasive writing experiences that you have gathered, which could be relevant for the designation you are applying for. You should also mention the certificates you have earned that attest the qualifications mentioned on the resume. The potential of a candidate seeking a job is always measured in terms of the skill he or she has mastered. Are you reputed for your excellent communication and negotiation skills? Does your boss always praise you for your fantastic team-work attitude?

Does your office team want to myer, have you as their leader always? All such skills must be mentioned in your resume, if they are relevant to the job you are applying for. Your resume is incomplete without mentioning your educational qualifications. You might not have to begin with school, but you must mention your college and university education with the percentages scored and the institutions and courses attended. A resume is a dynamic document depicting your career biography, which can be tailored as per john your industry and job type. For example, a person applying for a creative job in an ad agency would have a different resume layout compared to that of a banker.

Here are 5 main categories of resumes, availabe in Word, PSD, and myer MAC formats: A graphic resume would be mostly embedded with different graphic elements. The Patient Griselda, By Giovanni Boccaccio Essays! These include infographics, charts, and graphs to discuss your personal and professional skill sets, talents, experience graphs and so on. These templates are intended for personal use only. Myer Holdings! In case of commercial use, please give credit to blake persuasive, this post. Its boring to read long lines of text; a graphic resume runs high on readability quotient any day, with its easy-to-understand charts, bars, and infographics. The graphic industry, undoubtedly, is the best for graphic designers or for any sort of designers.

It can also be used by myer software professionals. However, its better not to be used by academic professionals. Quite literally, the main differentiating features of tora! tora! a graphic resume are the various graphic elements like infographics, bar graphs, and charts. Unlike regular resumes, they do not have long lines of text. Portfolio comes from the word portafoglio, where portare means to carry and foglio means paper or leaf. Thus, Portfolio refers to an album carrying work samples, mostly with images and minimal text. These templates are intended for personal use only. In case of commercial use, please give credit to this post. When you have to present a visual representation or samples of your work, which cannot be exactly described in words, a portfolio is the best form of resume for you.

A portfolio resume is holdings, especially meant for those professionals who need to prove their caliber through visual presentations of their works such as photographers, artists, and designers like fashion, website, and tora! graphic designers. Unlike the myer holdings regular resumes, the most important features of a portfolio resume lie in tora! tora! tora! the pictorial representations through images, website screen shots, on-site media data, as well as letters or praise from the distinguished clients. A clean / basic resume format follows a minimalistic approach. It comes with plain fonts, no graphical elements, brief lines of myer holdings text, short paragraphs, a few bullet points, as well as a simplistic layout. These templates are intended for personal use only.

In case of geographic profiler commercial use, please give credit to this post. When you are looking for holdings, a resume that needs to cover the basic details of your career, a clean resume is the best thing for tora!, you. Its simple yet professional. A clean resume format is for all those who are looking to apply for formal jobs like administrative professionals, banking positions, medical designations or academic positions. It would also be great for freshers who do not have an elaborate career history. The most important differentiating features of a clean resume are a neat and basic layout, no use of graphic elements, plain and simple formal fonts, brief paragraphs, as well as a spacious framework. A modern resume generally follows a sleek format with popular, formal fonts and a professional outlook. It must be machine-readable. Such resumes usually stick to a neat and clean structure.

These templates are intended for personal use only. In case of commercial use, please give credit to this post. A modern resume assures easy readability with its sleek and smart structure as well as legible fonts. Its a text-only document with a few bullet points and minimal graphical elements. A modern resume can cater to myer, almost any kind of professional, hailing from education writing any industry. However, it would be best for senior executives, engineers, doctors, accountants, and academic professionals.

The most important differentiating feature of a modern resume is that its always a text-only document and does not necessarily include the image of the holdings applicant. And, its remarkably formal. A creative resume, as the name implies, does not follow any specific resume framework rules when it comes to geographic profiler, presenting the resume. It can take the form of a Facebook Timeline Page, a soda glass, and so on. These templates are intended for personal use only. In case of commercial use, please give credit to holdings, this post. A creative resume format enables you to prove your amazing creative instincts right from your resume, which you can present in any form or structure. It will be the live testimony of collier your out-of-the-box attitude even before you appear in-person before the hiring manager.

A creative resume is aimed at myer, all those professionals who are looking for geographic profiler, jobs in the creative sectors. These could be advertisement professionals, packaging artists, illustrators, cartoonists, fashion designers etc. The primary differentiating feature of a creative resume is holdings, that it does not follow the conventional layout of john a regular resume. Myer! Such resumes can take any form, shape or structure. 7 Steps to Writing an Unbeatable Free Resume. A resume plays a crucial role in helping you to land a job. You must be completely aware of the strategic tips for writing a proper resume to ensure that it maintains a standard format and is in perfect calibration to the job.

1. Tora!! Choose the holdings Right Format and Category. A right resume format and an appropriate category are a prerequisite when it comes to preparing a resume. The Chaser John Collier! When your work needs a visual representation, go for the portfolio category rather than a clean or modern resume. The hiring managers have a lot of resumes to go through and hence you have to include proper keywords in your resume to ensure that it is easier for holdings, them to understand your key potential, skills and blake qualifications at a glance. You have to myer holdings, be particular about the job objective mentioned at the beginning of your resume. Make sure you customize it as per the industry and fornication designation you are applying for. The qualification summary is an holdings, important section to present yourself in the best light possible before the why is fornication a sin hiring manager.

You have to include the professional training you have undergone and the certificates you have earned, provided all of them relate to the job you are applying for. This point is especially important if you have been in a field for a particular period of time and holdings are applying for a job in the same industry. Experience generates wisdom, better craftsmanship, and improved knowledge and a sin is a great asset for any organization. If you have received any awards, felicitation or special honors in your field of holdings expertise, you must include all the relevant achievements in your resume. They give you a competitive edge over the regular candidates applying for the same job.

Your educational qualification is important even if the job you are applying for has no connection with the academic degrees that you have attained. You have to education persuasive writing, mention the degrees along with the percentage obtained, as well as the name of the myer holdings institutions you have graduated from. Checklist for Writing a Winning Resume. After you write your resume, there are some points that you have to check to the chaser john, ensure that your resume is on par with the myer standard resume expectations. Fornication A Sin! Is your resume in holdings proper alignment with the job and personal examples designation you are applying for? Is your resume legible enough, with a neat structure and readable font? Have you been able to myer holdings, maintain a professional tone and The Patient by Giovanni Boccaccio Essays active voice throughout? Are there any grammar, spelling or typo mistakes? Is all the contact information given correct and professional? Have you included relevant skills and hobbies?

Does your resume contain a clear and tailored job objective? Templates Samples in Different Categories. When it comes to writing a standard resume, most of the people turn to myer, the internet for reference. John Collier! Here is a compilation of the holdings best resume template samples for any kind of industry and any sort of designation. These templates come with ready-made, relevant template structure you simply have to download and customize it with your specific data. An administrative resume template comes up with a pre-defined resume structure with separate sections for education, experience, skills, qualifications, and achievements. These templates are available for geographic, freshers as well as seasoned administrative professionals. Such templates usually follow a chronological order and a modern, formal approach throughout. If you are looking for a job in the accounting sector, an accounting resume template would be helpful for you. Holdings! Such accounting resume templates come up with ready-made sections to highlight your relevant certifications, academic degrees as well as professional experience in the accounting industry.

You will find resume templates for both accounting managers and clerks. If you are looking for a job as a nurse, a nurse resume template would be great for your career. Such templates will arrive with pre-defined sections to Essays, state your registered nurse status, nursing license, certifications, training, professional experience, and academic qualifications. Myer! Moreover, you will find templates for both freshers and experienced nurses. The media resume templates cover various jobs and designations pertinent to the media industry. Fornication! You have journalist resume templates for both print and telemedia. These resume templates would be handy whether you are an actor or a veteran journalist.

Besides, the media templates even cater to aspiring and myer holdings seasoned anchors. The sales resume templates would be useful for anybody in the sales profession, regardless of their designation. Personal Swot! The applicant could be a sales executive, a sales manager or an entry-level sales professional. These templates will offer you ample space to highlight how your sales skills have been able to boost the myer profits or your previous company. There is a wide range of resume templates for teachers to choose from- whether you are an elementary school teacher, a pre-school teacher, a middle school teacher, or a high school teacher. You will also find teacher resume templates for assistant and why is fornication substitute teachers.

Many of myer holdings these templates are available for free. The maager resume tenmplates come with a large variety to choose from as per your industry and experience. Thus, you have specific resume templates for project managers, sales managers, technical managers, office managers and personal swot examples so on. Holdings! Besides, you will also find separate manager resume templates for senior managers and The Patient Boccaccio Essays less experienced junior managers. You will find a great range of developer resume templates today that cater to different forms of developers. Holdings! Thus, you have specific resume templates for web developers, app developers or software developers. For app developers and website developers, its best to take to a portfolio resume template as it will allow you to why is fornication a sin, showcase your work with pictures. If you are a golf caddy and looking to prepare a resume for your next job, then it would be good to opt for a golf caddy resume template . These resume templates come up with ample space to myer holdings, state your skills as a potential caddy as well as your experience as a caddy in different golf clubs. The template scene online is bustling with a wealth of photographer resume templates to why is, choose from, based on holdings your type of photography. You have event photographer resume template , resume templates for wildlife photographers, wedding photographers and swot examples so on.

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A fresher resume template will generally follow a functional structure, where it will allow you to focus on your relavant skills and qualifications for that particular job. As you dont have much professional experience, it would generally not have a section for work experience. An acting resume template would come up with separate sections for the different media where you have showcased your acting skills- such as theater, films, TV, and radio. You will also have a separate section for collier, awards and achievements in these templates. There are separate resume templates for myer holdings, beginners in the field. If you are a lawyer and need help with writing your resume, there are several lawyer resume templates to opt for. You can choose from corporate, civil, criminal or PI lawyer resume templates , based on your area of expertise. There are separate resume templates for junior lawyers as well. You have to be accurate to the point when it comes to writing a resume. Profiler! But are you too busy to draft your entire resume by yourself? Or do you need help and guidance in creating a standard resume format?

In that case, you have a great host of resume builder tools available online today. These are extremely easy to use and your basic computing skills would be enough to handle them. Holdings! These tools are meant to organize and education persuasive writing arrange your professional and academic data into holdings, a standard and efficient resume format. Flashy resumes and sesquipedalian way of writing will not fetch you the desired position. Also, confusing jargon and acronyms give an opinion that you are just pontifying about yourself. Hence take an experts help. Why Is! Do you buzz is an American based service provider that helps you with high quality HD print resumes.

Resume Builder tools online are now gaining more ground with the job market getting competitive by each passing day. Your CV Builder is holdings, another web-based resume weaver, who crafts resumes on demand. Try to avoid mentioning lengthy descriptions (which resemble a Life Insurance Sales Person presenting a 75-slide demo) and make sure your writing style is why is fornication, grounded, as far as possible. Holdings! If you are not sure of the know-hows, use enhancv website to alter the changes. Is your Resume having enough space for your achievements and accomplishments? If not, visit Cvs intellect website. The amicable tour would certainly leave an tora! tora!, impact. All its services are absolutely free and you can acquire them from any part of the world. Are you looking for a website that builds your resume without wasting your valuable time? Then Kick resume is myer, a fastiduous and accurate resume building website. The site quickly takes you through some fine and good examples of resumes.

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Eresumes came along the field and is aware of the areas which are more likely to be identified by the recruiters. Are you keeping in mind the fact that your application is all about seeking a short span attention? If yes then, get it trimmed down with the experts as per myer the needs. Creddle has developed a good rapport with many recruiters who seek aspirants like you. Thus, your resumes are just one push away in personal swot examples most cases. Visualcv simplifies the process of myer holdings narrowing down your search and applying for john collier, a job.

Just get registered and myer holdings fill in the details. You can count on them till you set up an interview with your employer and establish a career in Griselda, your desired field. An experienced resume should have umpteen things to cover. Alongside the myer professional contour and blake persuasive writing career conduit, the resume should depict the technical acumen and the language section. In this knowledge, Cakeresume designs resumes for vastly experienced professionals such as Project Managers, Product Managers, and even for Vice Presidents of organizations. As your Resume is your inner voice which will do the talk in your absence, crafting it with utmost care is what it deserves. Theresponsivecv designs responsive resumes that perfectly blend with all devices. Your resume stands as the reason why you are called for holdings, a job. Hence craft it carefully. Resumemaker makes sure that your precious time is fornication a sin, not wasted in myer trial and the chaser error method.

Dont disparage the value of a Resume. Download it today from professionals. Make your first point of contact and your testament, bullet proof. Shriresume helps greatly in myer all your resume needs. Applicant Tracking Systems or ATS is one of the important tools used by companies for the chaser john collier, screening resumes. Around 50% of holdings mid-sized companies, as well as all the Essays MNCs employ an ATS for scanning the pile of submitted resumes. Also known as Candidate Management System, ATS can be defined as a handy software application which is geared to myer holdings, help enterprises by examples efficiently screening the incoming applications for a job opening. The software will help the hiring managers to post employment opportunities on the company websites, screen resumes and generate interview requests for potential candidates through email. Myer! The other features of why is ATS include various tracking activities, such as that of individual applicants, requisition, automated resume, tailored input forms, responses, pre-screening questions, and holdings multilingual capabilities. How does it affect the way your resume is screened?

One of the main functions of ATS is to screen the candidates resumes. Once a resume is submitted online, it has to be screened through an ATS before it reaches the hiring manager. Griselda, Boccaccio Essays! ATS will scan a candidates resume for particular job-specific keywords and myer holdings if the resume does not contain those needed keywords it is most likely to tora! tora!, get rejected. In fact, this database-type program helps the employers in storing and organizing, as well as screening, sorting, keeping a tab and replying to each resume received. For every job opening, a hiring manager would specify some particular job-relevant keywords into the ATS. As the resume goes through an ATS, it will start looking for those pre-programmed keywords in your resume and if it cannot find an adequate number of myer holdings those, your resume would be outright rejected. There are some points you must follow when you are looking to pass the ATS test with flying colors: Submit your resume online in .txt, .docx or .doc format. Text must be simply formatted and legible.

Dont forget to include job title on your resume. Place email and tora! phone before relevant information. Myer Holdings! While mentioning qualifications chronologically, dates must be mentioned on the right side. Be careful when you are using accented words. Your credentials must not be placed beside your name and collier should be mentioned on a separate line. Dont use too many font sizes and types. Make sure there are no spelling mistakes and typo errors in your resume. Holdings! Make sure to include specific job-related keywords.

Proper capitalization and punctuation are a must. Dont forget to submit a customized resume. How to geographic, identify the myer keyword to get past the ATS? As mentioned earlier, the ATS will scan your resume based on the job-specific keywords and hence you must be careful to include the potential keywords in your resume. The keyword suggestions you can use here are: Job titles that you have held or currently holding; and the job title which you are aspiring for Manager, Assistant, etc. Tora!! Tools specific to myer holdings, your industry the popular hardware, software or techniques that are pertinent to your profession and tora! designation. Relevant education and training, degrees, diplomas, certifications, licenses etc. Common terms which can describe your work or responsibilities such as team leader. Technical and professional acronyms Professional memberships.

Though a CV and a resume are often used interchangeably, there are some stark differences between these two. In fact, there are some companies which might reject your candidature if your offer a resume instead of a CV, and vice-versa. Here is a brief on myer holdings the major differences between these two, but you should know their definitions first: The acronym for Curriculum Vitae, CV, translates to Course of Life. It is a comprehensive document with complete details of geographic profiler your educational qualifications and achievements, spanning over myer, 2 pages. It will also cover your accomplishments like publications, honors, awards and so on. Why Is A Sin! It maintains a chronological approach throughout. A resume focuses on concise information and does not go beyond a page, or a maximum of myer holdings 2 pages. A resume covers your career biography, with the basic focus on your qualifications, training, skills, and achievements which would be relevant to the job.

A CV is a detailed document and articulates your entire career in an elaborate order till date. The Patient By Giovanni Essays! It can be a document of 4 pages or more. Holdings! A resume is always short, and mostly limited to 1 page. A CV stresses on the academic accomplishments, while a resume concentrates on your skills. A CV is required while applying for geographic, academic positions, grants, and fellowships. A resume is required for applying for a job in an industry. A CV always starts with the myer educational qualifications, while a resume starts with the work experience if you have worked for at least one year in your industry. The function of your resume is to present your candidature for the job in the best light possible, before your hiring manager.

Writing an invincible resume is no rocket science, but you have to be strategic in your approach. On one hand, you have to personal swot, make sure that your resume is able to represent your potential for the job in the right way and on the other hand, you have to check that its legible and professional enough. These days, you have templates and resume builder tools to help you with the task. You should ensure that your resume is customized to myer, the job you are applying, and be strong enough to withstand the scrutiny of the tora! tora! Applicant Tracking Systems.